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| MM74HCT138 3-to-8 Line Decoder February 1984 Revised February 1999 MM74HCT138 3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits feature high noise immunity and low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. The MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading decoders. The decoders' output can drive 10 low power Schottky TTL equivalent loads and are functionally and pin equivalent to the 74LS138. All inputs are protected from damage due to static discharge by diodes to VCC and ground. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Features s TTL input compatible s Typical propagation delay: 20 ns s Low quiescent current: 80 A maximum (74HCT Series) s Low input current: 1 A maximum s Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HCT138M MM74HCT138SJ MM74HCT138MTC MM74HCT138N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP (c) 1999 Fairchild Semiconductor Corporation DS005362.prf www.fairchildsemi.com MM74HCT138 Truth Table Inputs Enable G1 X L H H H H H H H H H = HIGH Level L = LOW Level X = Don't Care Note 1: G2 = G2A + G2B Outputs Select C X X L L L L H H H H B X X L L H H L L H H A X X L H L H L H L H Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L G2 (Note 1) H X L L L L L L L L Logic Diagram www.fairchildsemi.com 2 MM74HCT138 Absolute Maximum Ratings(Note 2) (Note 3) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 4) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C 600 mW 500 mW -0.5 to +7.0V -1.5 to VCC +1.5V -0.5 to VCC +0.5V 20 mA 25 mA 50 mA -65C to +150C Recommended Operating Conditions Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 3: Unless otherwise specified all voltages are referenced to ground. Note 4: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C. Max 5.5 VCC +85 Units V V C 4.5 0 -40 DC Electrical Characteristics VCC = 5V 10% (unless otherwise specified) Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| = 20 A |IOUT| = 4.0 mA, VCC = 4.5V |IOUT| = 4.8 mA, VCC = 5.5V VOL Maximum LOW Level Voltage VIN = VIH or VIL |IOUT| = 20 A |IOUT| = 4.0 mA, VCC = 4.5V |IOUT| = 4.8 mA, VCC = 5.5V IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN = VCC or GND, VIH or VIL VIN = VCC or GND IOUT = 0 A VIN = 2.4V or 0.5V (Note 5) Note 5: This is measured per input pin. All other inputs are held at VCC or ground. Conditions TA = 25C Typ 2.0 0.8 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 2.0 0.8 2.0 0.8 Units V V VCC 4.2 5.2 0 0.2 0.2 VCC- 0.1 3.98 4.98 0.1 0.26 0.26 0.1 8.0 0.3 VCC- 0.1 3.84 4.84 0.1 0.33 0.33 1.0 80 0.4 VCC- 0.1 3.7 4.7 0.1 0.4 0.4 1.0 160 0.5 V V V V V V A A mA 3 www.fairchildsemi.com MM74HCT138 AC Electrical Characteristics TA = 25C, VCC = 5.0V, tr = tf = 6 ns, CL = 15 pF (unless otherwise specified) Symbol tPHL tPLH tPHL tPLH tPHL tPLH Parameter Maximum Propagation Delay, A, B, or C to Output Maximum Propagation Delay, A, B, or C to Output Maximum Propagation Delay, G1 to Y Output Maximum Propagation Delay, G1 to Y Output Maximum Propagation Delay, G2A or G2B to Y Output Maximum Propagation Delay, G2A or G2B to Y Output Conditions Typ 20 13 14 13 17 13 Guaranteed Limit 35 25 25 25 30 25 Units ns ns ns ns ns ns AC Electrical Characteristics VCC = 5V 10%, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol tPHL tPLH tPHL tPLH tPHL tPLH tTHL, tTLH CIN CPD Parameter Maximum Propagation Delay A, B, or C to Output Maximum Propagation Delay A, B, or C to Output Maximum Propagation Delay G1 to Y Output Maximum Propagation Delay G1 to Y Output Maximum Propagation Delay G2A or G2B to Y Output Maximum Propagation Delay G2A or G2B to Y Output Maximum Output Rise and Fall Time Input Capacitance Power Dissipation Capacitance (Note 6) 55 5 10 10 pF pF 15 19 22 ns 18 30 38 45 ns 23 35 43 52 ns 20 30 38 45 ns 17 30 38 45 ns 18 30 38 45 ns Conditions TA = 25C Typ 24 40 TA = -40 to 85C TA = -55 to 125C Guaranteed Limits 50 60 Units ns Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 MM74HCT138 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HCT138 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 MM74HCT138 3-to-8 Line Decoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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